Following are the details: : Start signal SCL High SDA High to Low
The Start signal appears at High to Low transition on the SDA line when SCL is High. : Write Slave Address The Write Slave Address is 20h, 22h, 24h or 26h, : Read Slave Address The Read Slave Address is 21h, 22h, 25h or 27h. : Value of the AL240 register index. (c)2004 by AverLogic Technologies, Corp.Version 1.0 March 8, 2005 18
AL240
: Acknowledge stage The host (master) generates acknowledge-related clock pulse. During the acknowledge clock pulse, the host must release the SDA line (to High) in order that AL240 (slave) can pull down the SDA. : Non-Acknowledged stage The host (master) generates acknowledge-related clock pulse. The host also releases the SDA line (to High) during the acknowledge clock pulse, but the AL240 does not pull it down during this stage. : Data byte written to or read from the register index In read operation, the host must release the SDA line (to High) before the first clock pulse is transmitted to the AL240.

: Stop signal SCL High SDA Low to High
The Stop signal appears at Low to High transition on the SDA line when SCL is High. Suppose data F0h is to be written to register 0Fh using write slave address 24h, the timing is as follows:
S ta rt S la v e a d dr = 24 h Ack In d e x = 0 F h Ack D at a = F 0 h Ack S to p
S DA S CL
Figure 4: Two-wire Serial Bus Write Timing Suppose data is to be read from register 55h using read slave address 25h, the timing is as follows:
Start Slave a ddr = 24h Ack Ind ex = 55h Ack R e a d sla ve a ddr = 25 h NAck Ack D a ta re a d cycle Stop
S ta rt
SDA S CL
Figure 5: Two-wire Serial Bus Read Timing
(c)2004 by AverLogic Technologies, Corp.Version 1.0
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AL240
8.10 Output Format The AL240 supports 8-bit YCbCr 4:2:2 digital formats along with LLC (27Mhz) line-lock clocks for output. The ITU-R BT.656 standard is embedded in output data. The internal output format control register needs to be set for proper output. The register value vs. output format and corresponding output bus interface are described in the following tables. Register Value B1h<3:0> 000x Output ITU-R BT. 656 (8-bit. hsync & vsync can be output from RTSO[4:0] pins).
And corresponding data output mapping is indicated as following. DO[7:0] Input/Output Pin Mappings 000X Pin # 656 output 12 YCbCr7 13 YCbCr 6 14 YCbCr 5 15 YCbCr 4 19 YCbCr 3 20 YCbCr 2 21 YCbCr 1 22 YCbCr 0 36 RTSO[4] 37 RTSO[3] 27 RTSO[2] 26 RTSO[1] 25 RTSO[0] Table below is the output video standard and their specification.
STANDARDS NTSC (M, 4.43) PAL (B,D,G,H,I) PAL (M) PAL (N) SECAM LINE RATE (KHz) 15.73426 15.625 15.73426 15.625 15.625 PIXEL TOTAL PER LINE 858 864 858 864 864 ACTIVE PIXEL PER LINE 720 720 720 720 720 PIXEL CLOCK RATE 27 27 27 27 27
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AL240
The 8-bit ITU-R BT.656 output format is indicated by the following figure,
BT.656 EAV Code BT.656 SAV Code
DO[7:0] B Y R Y F 0 4
C
C
F
0
0 0
X Y
8 0
1 0
8 0
1 0
8 0
1 0
F F
0 0
0 0
X Y
C Y B
C Y R
C Y B
C Y R
Y
C Y B
C Y R
268 BLANKING
4
1440 ACTIVE
HDE
Figure 6: ITU-R.BT656 Timing reference codes Each timing reference code consists of a four word sequence in the following format: FF 00 00 XY (in hexadecimal notation). Codes "FF 00 00" are fixed preamble of timing code and fourth byte contains timing information as defined in following, Where, F (Field): 0 - filed 1; 1 - filed 2 V (Blanking): 0 - elsewhere; 1 - during filed blanking H (SAV/EAV): 0 - in SAV; 1 - in EAV P0, P1, P2, P3: Protection bits XY bit number Function 0 1 2 3 4 5 6 7 7 Fixed 1 1 1 1 1 1 1 1 6 F 0 0 0 0 1 1 1 1 5 V 0 0 1 1 0 0 1 1 4 H 0 1 0 1 0 1 0 1 3 P3 0 1 1 0 0 1 1 0 2 P2 0 1 0 1 1 0 1 0 1 P1 0 0 1 1 1 1 0 0 0 P0 0 1 1 0 1 0 0 1
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AL240
9 Register Definition
9.1 Register Set Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h~1B 1Ch ~ 1Fh 20h 21h 22h 23h 26h 27h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h R/W Default Description R/W 00h System configuration 0 R/W 01h System configuration 1 R/W 4Eh AGC configuration R/W 00h YC separation control R/W DDh Luma AGC target value R/W 32h Noise threshold R/W 00h ADC swap R/W A0h Output control R/W 80h Luma contrast adjustment R/W 20h Luma brightness adjustment R/W 80h Chroma saturation adjustment R/W 00h Chroma Hue adjustment R/W 8Ah Chroma AGC target value R/W 07h Chroma kill control R/W 2Ch Chroma auto position control R/W 0Ah For manufacture use only R/W 09h For manufacture use only R/W 10h Blue screen Y value R/W B4h Blue screen Cb value R/W 80h Blue screen Cr value R/W 20h For manufacture use only R/W 04h For manufacture use only R/W 0Bh For manufacture use only R/W 00h Chroma DTO increment [29:0] R/W 00h For manufacture use only R/W 3Eh For manufacture use only R/W 3Eh For manufacture use only R/W 00h For manufacture use only R/W 80h For manufacture use only R/W 2Dh For manufacture use only R/W 50h For manufacture use only R/W D6h For manufacture use only R/W 4Eh For manufacture use only R/W 32h For manufacture use only R/W 46h For manufacture use only R/W 82h Active video horizontal start time R/W 50h Active video horizontal width R/W 22h Active video vertical start time R/W 61h Active video vertical height March 8, 2005 22 Register Name CTRL0 CTRL1 CTRL2 YCSEPCTRL HAGC NOISETH ADCSWAP OUTPUTCTRL LUMAC LUMAB CHROMAS CHROMAHPHASE CHROMAAGC CHROMAKILL CHROMAPOS AGCPEAKNOM AGCPEAKCTRL BLUESCRY BLUESCRCB BLUESCRCR HDETCLAMPLV LOCKCOUNT HLOOPMAX CHROMADTOINC HSYNCDTOINC HSYNCTIME HSYNCOFFSET HSYNCSTART HSYNCEND HSYNCRISSTART HSYNCRISEND HSYNCFLTSTART HSYNCFLTEND CHROMASTART CHROMAEND HACTIVESTART HACTIVEWIDTH VACTIVESTART VACTIVEHEIGHT
(c)2004 by AverLogic Technologies, Corp.Version 1.0
AL240
VSYNCHMIN VSYNCHMAX VYSNCAGCMIN VSYNCAGCMAX VSYNCVBIMIN VYSNCVBIMAX VYSNCCTRL VSYNTIMECNT STATUS1 STATUS2 STATUS3 MUXANALOG MUXDIGITAL SOFTRST VBICODECTRL VBISTARTCODE VBIDATAHL VBILINE7 VBILINE8 VBILINE9 VBILINE10 VBILINE11 VBILINE12 VBILINE13 VBILINE14 VBILINE15 VBILINE16 VBILINE17 VBILINE18 VBILINE19 VBILINE20 VBILINE21 VBILINE22 VBILINE23 VBILINE24 VBILINE25 VBILINE26 VBIIGAIN0 VBIIGAIN1 CCDTOINC
32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h&5Ah
R/W R/W R/W R/W R/W R/W R/W R/W R R R R/W R/W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
F0h 0Eh ECh 10h F0h 0Eh 40h 0Ah 00h 00h 00h 00h 00h 01h 04h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
For manufacture use only For manufacture use only For manufacture use only For manufacture use only For manufacture use only For manufacture use only For manufacture use only Vsync time constant Status register 1 Status register 2 Status register 3 For manufacture use only For manufacture use only Soft reset Teletext VBI frame code control Teletext VBI Frame code VBI data high level VBI data type configuration for line 7 VBI data type configuration for line 8 VBI data type configuration for line 9 VBI data type configuration for line 10 VBI data type configuration for line 11 VBI data type configuration for line 12 VBI data type configuration for line 13 VBI data type configuration for line 14 VBI data type configuration for line 15 VBI data type configuration for line 16 VBI data type configuration for line 17 VBI data type configuration for line 18 VBI data type configuration for line 19 VBI data type configuration for line 20 VBI data type configuration for line 21 VBI data type configuration for line 22 VBI data type configuration for line 23 VBI data type configuration for remaining lines VBI data type configuration for remaining lines VBI data type configuration for remaining lines VBI loop filter gain for close-caption& teletext VBI loop filter gain for wss625 DTO incremental value for close-caption clock March 8, 2005 23
(c)2004 by AverLogic Technologies, Corp.Version 1.0
AL240
TELDTOINC WSSDTOINC CCFSTART WSSFSTART TELFSTART CCDATA1 CCDATA2 VBINOISETH VBISTATUS CCSTART WSSSTART TELSTART HSSTART HSWIDTH VSSTART VSWIDTH WSSDATA2 WSSDATA1 WSSDATA0 HSDTOINCSTATUS CSDTOINCSTATUS AGCSTATUS CMAGSTAUS CGAINSTATUS CORDICFSTATUS NOISESTATUS COMBFLTTH COMBFLTCONFIG CHROLKCONFIG COMBFLTTH1 COMBFLTTH2 COMBFLTTH3 COMBFLTTH4 CHROLOOPFLT CHROHRECTRL CPUMPDLYCTRL CPUMPADJUST CPUMPDLY VERSION OFORMAT
5Bh&5Ch 5Dh&5Eh 5Fh 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h~73h 74h~77h 78h&79 7Ah 7Bh&7Ch 7Dh 7Fh 80h 82h 83h 84h 85h 86h 87h 8Ah 8Bh 8Dh 8Eh 8Fh B0h B1h
R/W R/W R/W R/W R/W R R R/W R R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W
00h 00h 00h B4h 00h 00h 00h 00h 00h 00h 64h 5Ah 01h 40h 01h 04h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 04h 42h 6Fh 07h 20h 03h 10h 0Ah 01h 28h C8h B9h 42h 10h
recovery circuit DTO incremental value for teletext clock recovery circuit DTO incremental value for wss625 clock recovery circuit Frame start for the close caption Frame start for wss625 Frame start for TELETEXT Close captioning data byte 1 Close captioning data byte 2 Noise level for the VBI line VBI data status Close caption start WSS625 start Teletext start Output hsync start position Output hsync width Output vsync start line Output vsync width Wide screen signaling data byte 2 Wide screen signaling data byte 1 Wide screen signaling data byte 0 Hsync DTO increment status Chrom DTO increment status AGC gain value Chroma magnitude Chroma gain SECAM cordic frequency Noise status Comb filter threshold Comb filter configuration For manufacture use only For manufacture use only For manufacture use only For manufacture use only For manufacture use only For manufacture use only For manufacture use only For manufacture use only For manufacture use only For manufacture use only Chip version Digital output format control March 8, 2005 24
(c)2004 by AverLogic Technologies, Corp.Version 1.0
AL240
RTSO[0]&TSTPAT RTSO[1] RTSO[2]
B2h B3h B4h
R/W R/W R/W
02h 03h 04h
RTSO[3]
B5h
R/W
07h
RTSO[4]
B6h
R/W
08h
AFEIN&FSW
B7h[4]
R/W
00h
PLLCTRL 0 PLLCTRL1 PLLCTRL2 LLCDTOINC 3 LLCDTOINC 2 LLCDTOINC 1 LLCDTOINC 0
B8h B9h BAh BBh BCh BDh BEh
R/W R/W R/W R/W R/W R/W R/W
00h 22h 10h 38h E3h 8Eh 38h
FIFOGAIN
BFh
R/W
03h
DCRSTOCTRL 0 DCRSTOCTRL 1 MANUALGAIN PBKILLTH DCRSTOHMID MINSYNCHEIGHT SLEWCTRL
C0h C1h C2h C3h C4h C5h C8h
R/W R/W R/W R/W R/W R/W R/W
D4h 1Bh 40h C0h 7h 10h 51h
Control RTSO[0] output signal as Hsync, Vsync, Field or others. Default output signal for RTSO[0] is Hsync signal. Control RTSO[1] output signal as Hsync, Vsync, Field or others. Default output signal for RTSO[1] is Vsync signal. Control RTSO[2] output signal as Hsync, Vsync, Field or others. Default output signal for RTSO[2] is Field signal. Control RTSO[3] output signal as Hsync, Vsync, Field or others. Default output signal for RTSO[0] is "Hactive ANDs Vactive" signal. Control RTSO[4] output signal as Hsync, Vsync, Field or others. Default output signal for RTSO[4] is VBI valid signal. Selects four analog inputs AI0, AI1, AI2 and AI3 for the combinations of 4 CVBS, 2 Svideo, 2 CVBS/1 S-video or 1 YPbPr inputs. And enable FSW0 and FSW1 Hardware switching control signals output from RTSO[3] and RTSO[4] respectively. PLL enable/power down and LLC circuit divider values For manufacture use only PLL feedback divider settings LLC DTO increment value <31:24> LLC DTO increment value <23:16> LLC DTO increment value <15:8> (unused) LLC DTO increment value <7:0> (unused) 4 bit <3:0> FIFO gain level adjustment Max: 8 Min: 0 For FIFO level > 8: Fixed DTO, LLC output frequency depend on the value of registers BBh and BCh DC restore circuit filter and gain control DC restore circuit accumulate width adjustment Manual Gain adjustment For manufacture use only Set the horizontal mid-point used to reset the DC-restore accumulators. For manufacture use only For manufacture use only March 8, 2005 25
(c)2004 by AverLogic Technologies, Corp.Version 1.0
AL240
SLEWINC SLEWPERIOD SLEWPOLTH FIFOLEVEL AFETSTMODCTRL1 AFETSTMODCTRL2 DATASWAP YCGAIN WRITEENABLE
C9h ~ CBh R/W CCh CDh D0h D2h D3h D4h D5h FEh
3126EA For manufacture use only h R/W 10h For manufacture use only R/W C8h For manufacture use only Output data FIFO level status; Read only value R around 0x80h while DTO lock R/W 10h For manufacture use only R/W FCh For manufacture use only R/W 00h Output data swap R/W 05h Adjust PGA amplifier gain level R/W 00h Register write enable
9.2
Register Description
INDEX Register Description (HEX) Register Name BITS Standard Control Register 00
Function Description
System Configuration 0 (R/W) [CTRL0] yc_src <0> Input video format 0 Composite (default) 1 S-Video (separated Y/C) colour_mode <3:1> Video color standard 000 NTSC (default) 001 PAL (I,B,G,H,D,N) 010 PAL (M) 011 PAL (CN) 100 SECAM vline_625 <4> The number of scan lines per frame 0 525 (default) 1 625 hpixel <6:5> Output display format 00 NTSC, PAL(M); 858 pixels/line (default) 01 PAL(B,D,G,H,I,CN), SECAM; 864 pixels/line 10 NTSC Square Pixel, PAL(M) Square Pixel; 780 pixels/line 11 PAL(B,D,G,H,I,N) Square Pixel; 944 pixels/line hv_delay <7> Emulate the HV-delay found on Sony studio monitor 0 Disabled (default) March 8, 2005 26
(c)2004 by AverLogic Technologies, Corp.Version 1.0
AL240
1 01
Enabled
System Configuration 1 (R/W) [CTRL1] ped <0> Enables black level correction for 7.5 blank-toblank setup (pedestal) 0 No pedestal subtraction 1 Pedestal subtraction (default) chroma_burst5to1 <1> The burst gate width 0 0 5 subcarrier clock cycles (default) 1 10 subcarrier clock cycles chroma_bw_lo <3:2> Chroma low pass filter to wide or narrow 00 Narrow 01 Wide 10 Extra wide luma_notcha_bw <5:4> Luma notch width 00 None (default) 01 Narrow 10 Medium 11 Wide Reserved <7:6> Default `000' for normal operation AGC Configuration (R/W) [CTRL2] hagc_en <0> The luma/composite AGC enable. If disabled, then the AGC target (Register 04h) is used to drive the AGC gain directly. 0 Off 1 On (default) cagc_en <1> The chroma AGC enables. If disabled, then the AGC target is used to drive the AGC gain directly. 0 Off 1 On (default) agc_half_en <2> The half gain mode enable, when unlocked, for the analog front end. 0 Off 1 On (default) dagc_en <3> The digital AGC enable. The digital AGC is used in series with the analog gain. 0 Off 1 On (default) dc_clamp_mode <5:4> The analog front end DC clamping mode 00 Auto; use backporch when a signal exists; use synctip if no signal exists (default) 01 Backporch only 10 Synctip only March 8, 2005 27
02
(c)2004 by AverLogic Technologies, Corp.Version 1.0
AL240
mv_hagc
<6>
hagc_field
<7>
11 Off Automatically reduces the gain (set in Register 4) by 25% when macro-vision encoded signals are detected 0 Off 1 On (default) The gain update 0 Off (default); updated once per line after DC clamping 1 On; updated once per field at the start of vertical blank
YC-Separation Control Registers 03 YC Separation Control (R/W) [YCSEPCTRL] adaptive_mode <2:0> Composite signal's Y/C separation adaptive mode before color demodulation. 000 Fully adaptive (default) 001 Vertical adaptive (vertical only) 010 5-tap adaptive comb filter (PAL mode only) 011 Basic luma notch filter mode (for very noisy and unstable pictures) 100 Simple 2-tap comb 101 Simple 3-tap comb 110 5-tap hybrid adaptive comb filter (PAL mode only) colour_trap <3> Enables the notch-filter at the luma path after the comb filter. This filter can be turned on or off irrespective of the adaptive mode setting 0 Disabled (default) 1 Enabled Reserved <7:4> Reserved
Horizontal Acquisition Registers 04 Luma AGC Value (R/W) [HAGC] hagc <7:0> Luma AGC target value. The gain of the AGC is modified until the horizontal sync height is equal to this value. Standard Programming Value
NTSC M NTSC J PAL B,D,G,H,I, COMB N, SECAM PAL M,N NTSC M (MACROVISIOIN) DDh (221d) (default) CDh (205d) DCh (220d) DDh (221d) A6h (166d)
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AL240 PAL B,D,G,H,I, COMB N (MACROVISION) AEh (174d)
Note: * When a MacroVision signal is detected, luma AGC target value is automatically reduced by 25%. * If "hagc_en" (02h<0>) is "0", then "hagc" is used to directly drive the analog gain. In this case, a value of 64 represents a unity gain, 32 represents a one-half gain, and 128 denotes a double gain. 05 Noise Threshold (R/W) [NOISETH] noise_thresh <7:0> This value sets the noise value at which the circuit considers a signal noisy. The detected noise value may be read back through register 7Fh ("status_noise"). If the detected noise value is greater than "noise_thresh", then register 3Ch<3> ("noisy") is set. Larger values of "status_noise" indicate noisier signals, so larger values of "noise_thresh" decreases the likelihood of "noisy" being set while smaller values of "noise_thresh" increases the likelihood of "noisy" being set. (default = 32h) ADC Swap (R/W) [ADCSWAP] Reserved <4:0> Reserved adc_cbcr_pump_s <5> Swap the Pb/Pr charge pump pairs to the analog wap front-end 0 Disabled (default) 1 Enabled adc_input_swap <6> Swap the MSBs and LSBs from the analog frontend's ADC 0 Disabled (default) 1 Enabled adc_updn_swap <7> Swap the DC clamp up/down controls to the analog front-end. 0 Disabled (default) 1 Enabled
06
Output Control Register 07 Output Control (R/W) [OUTPUTCTRL] yc_delay <3:0> This 2's complement number controls the output delay between luma and chroma. Negative values shift luma outputs to the left while positive values shift luma values to the right. The range is [-5, 7]. Default = 0 March 8, 2005 29
(c)2004 by AverLogic Technologies, Corp.Version 1.0
AL240
blue-mode
cbcr_swap Reserved
<5:4> Blue screen mode control 00 Disabled 01 Enabled 10 Auto (default) 11 Reserved <6> Swap Cb/Cr output 0 Don't swap Cb/Cr (default) 1 Swap Cb/Cr <7> Reserve
Luma Adjustment Registers 08 Luma Contrast Adjustment (R/W) [LUMAC] contrast <7:0> The adjustable gain to the luma output path. (default = 80h) Luma Brightness Adjustment (R/W) [LUMAB] brightness <7:0> The adjustable brightness level to the luma output path. This value is offset by -32, i.e., a value of 32 (default) implies a brightness level of 0, and a value of 0 implies a brightness level of -32.
09
Chroma Adjustment Registers 0A 0B Chroma Saturation Adjustment (R/W) [CHROMAS] saturation <7:0> Color saturation adjustment value (default = 80h) Chroma Hue Phase Adjustment (R/W) [CHROMAHPHASE] hue <7:0> This 2's complement number adjusts the hue phase offset (default = 0h) Chroma AGC (R/W) [CHROMAAGC] cagc <7:0> Chroma AGC target (default = 8Ah) Chroma Kill (R/W) [CHROMAKILL] chroma_kill <3:0> Chroma kill level (default = 7h) hlock_ckill <4> When set, chroma is killed whenever horizontal lock is lost (default = 0h) vbi_ckill <5> When set, chroma is killed during VBI (default = 0h) user_ckill_mode <7:6> User chroma kill mode 00 Auto hardware chroma kill (default) 01 Forces chroma kill on 10 Forces chroma off
0C 0D
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AL240
0F
Chroma Autoposition (R/W) [CHROMAPOS] cautopos <4:0> The chroma burst gate position relative to the auto centre position (default = 0Ch) fixed_burstgate <5> When set, this bit disables the burst gate autopositon. The manual burstgate window position is defined by the burst_gate_start(2Ch) and burst_gate_end(2Dh) register. (default = 1h) <7:6> Reserved
Blue Screen 12 Blue Screen Y (R/W) [BLUESCRY] blue_screen_y <7:0> This register controls the blue screen (no video) luma value. The range is [16,235]. (default = 10h) Blue Screen Cb (R/W) [BLUESCRCB] blue_screen_cb <7:0> This register controls the blue screen (no video) Cb chroma value. The range is [16,240] (default = B4h) Blue screen Cr (R/W) [BLUESCRCR] blue_screen_cr <7:0> This registers controls the blue screen (no video) Cr chroma value. The range is [16,240]. (default = 80h)
13
14
Chroma DTO Registers Note: Following formula applies to determine the setting values of chroma DTO registers, cdto_inc = 4fSC / f INPUT x 230 , where fSC is the chroma sub-carrier frequency Where, fINPUT: is 20Mhz input clock 4fSC is sub-carrier frequency. And their corresponding frequencies in different standard are, Standard NTSC 3.58 NTSC 4.43 PAL B,D,G,H,I,N PAL M PAL CN SECAM 18 4fSC (Mhz) 14.31818182 17.734475 17.734475 14.30244596 14.328225 17.144
Chroma DTO Increment [29:24] (R/W) [CHROMADTOINC] cdto_inc <5:0> These bits contain bits [29:24] of the 30-bit-wide March 8, 2005 31
(c)2004 by AverLogic Technologies, Corp.Version 1.0
AL240
Reserved cdto_fixed
<6> <7>
chroma DTO increment Reserved Fixes the chroma DTO at its centre frequency 0 Disabled (default) 1 Enabled
19
Chroma DTO Increment [23:16] (R/W) [CHROMADTOINC] cdto_inc <7:0> BitS <23:16> of 30-bit-wide chroma DTO increment Chroma DTO Increment [15:8] (R/W) [CHROMADTOINC] cdto_inc <7:0> Bit <15:8> of 30-bit-wide chroma DTO increment Chroma DTO Increment [7:0] (R/W) [CHROMADTOINC] cdto_inc <7:0> Bit <7:0> of 30-bit-wide chroma DTO increment Active Video Horizontal Start Time (R/W) [ACTIVEHSTART] hactive_start <7:0> This bits control the active video line time interval. This specifies the beginning of active line. This register is used to centre the horizontal position, and should not be used to crop the image to a smaller size. (default =82h) Active Video Horizontal Width (R/W) [HACTIVEWIDTH] hactive_width <7:0> The active video line time interval control. It specifies the width of the active line, and should not be used to crop the image to a smaller size. The value 640 is added to this register. (default = 50h (80) 640+80 = 720)
1A 1B
2E
2F
Vertical Sync and Field Detection Registers 30 Active Video Vertical Start (R/W) [VACTIVESTART] vactive_start <7:0> Controls the first active video line in a field. It specifies the number of half-lines from the start of a field. (default = 22h) Active Video Vertical Height (R/W) [VACTIVEHEIGHT] vactive_height <7:0> The active video height control. It specifies the height by the number of half-lines. The value 384 is added to this register. (default = 61h (97) 97+394 = 481 half-lines)
31
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March 8, 2005
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AL240
39
Vsync Time Constant (R/W) [VSYNCTIMECNT] vloop_tc <1:0> Vertical PLL time constant 00 Fast. Only useful if the vloop_cntl register is not 11. Internal values are 2 and 1. 01 Moderate. Internal values are 1 and 1/4. 10 Slow. Internal values are 1/2 and 1/16 (default) 11 Very slow. Most useful for noisy signals. Internal values are 1/4 and 1/2. field_detect_mode <3:2> The field detection logic control. (default = 2) vodd_delayed <4> Delays detection of odd field by 1 vertical line 0 Disabled (default) 1 Enabled veven_delayed <5> Delays detection of even field by 1 vertical line 0 Disabled (default) 1 Enabled flip_field <6> Flips even/odd fields 0 Disabled 1 Enabled field_polarity <7> Output field polarity 0 Field = 1 for odd fields, field = 0 for even fields (default) 1 Field = 0 for odd fields, field = 1 for even fields Status Register 1 (R) [STATUS1] no_signal <0> No signal detection 0 Signal detected 1 No signal detected hlock <1> Horizontal line locked 0 Unlocked 1 Locked vlock <2> Vertical lock 0 Unlocked 1 Locked chromalock <3> Chroma PLL locked to color burst 0 Unlocked 1 Locked Reserved <7:4> Reserved Status Register 2 (R) [STATUS2] proscan_detected <0> Progressive scan detected 0 Undetected 1 Detected Reserved <7:1> Reserved March 8, 2005 33
3A
3B
(c)2004 by AverLogic Technologies, Corp.Version 1.0
AL240
3C
Status Register 3 (R) [STATUS3] PAL_detected <0> PAL Color Mode detected SECAM_detected <1> SECAM Color Mode detected 625lines_detected <2> 625 Scan Lines detected noisy <3> Noisy signal detected. It is set when the detected noisy value (status register 7Fh) is greater than the value programmed into the "noise_thresh" register (05h). vcr <4> VCR detected vcr_trick <5> VCR Trick-Mode detected vcr_ff <6> VCR Fast-Forward detected vcr_rew <7> VCR Rewind detected
Reset Register 3F Reset Register (W) [SOFTRST] soft_rst <0> Soft Reset 0 Normal operation 1 Software reset Reserved <7:1> Reserved
VBI Decoder Registers 40 Teletext VBI Frame Code Register (R/W) [VBICODECTRL] vbi_en <0> VBI decoder enable 0 Off (default) 1 On vbi_st_err_ignored <1> When this is "1", it will allow one bit error in the start code detection. When this bit is "0", all the start-code-bits must be correct during VBI line detection 0 Off (default) 1 On adap_slvl_en <2> Adaptive slicer enables. When it is enabled, the slicer level is determined by the built-in adaptive slicer generator. When is disabled, the slicer level is specified in the vbi_data_hlvl register. 0 Off 1 On (default) Reserved <7:3> Reserved Teletext VBI Frame Code Register (R/W) [VBISTARTCODE] Strart_code <7:0> The Frame Code used in the teletext for byte synchronization
41
(c)2004 by AverLogic Technologies, Corp.Version 1.0
March 8, 2005
34
AL240
42 43
Data High Level Register (R/W) [VBIDATAHL] vbi_data_hlvl <7:0> The VBI data high level VBI Data Type Configuration Register For Line 7 (R/W) [VBILINE7] vbil7o <3:0> Set VBI data type for odd field vbil7e <7:4> Set VBI data type for even field (Line 270 for 525 system. Line 320 for 625 system) VBI Data Type Configuration Register for Line 8 (R/W) [VBILINE8] vbil8o <3:0> Set VBI data type for odd field vbil8e <7:4> Set VBI data type for even field (Line 271 for 525 system. Line 321 for 625 system) VBI Data Type Configuration Register for Line 9 (R/W) [VBILINE9] vbil9o <3:0> Set VBI data type for odd field vbil9e <7:4> Set VBI data type for even field (Line 272 for 525 system. Line 322 for 625 system) VBI Data Type Configuration Register for Line 10 (R/W) [VBILINE10] vbil10o <3:0> Set VBI data type for odd field vbil10e <7:4> Set VBI data type for even field (Line 273 for 525 system. Line 323 for 625 system) VBI Data Type Configuration register Line 11 (R/W) [VBILINE11] vbil11o <3:0> Set VBI data type for odd field vbil11e <7:4> Set VBI data type for even field (Line 274 for 525 system. Line 324 for 625 system) VBI Data Type Configuration register Line 12 (R/W) [VBILINE12] vbil12o <3:0> Set VBI data type for odd field vbil12e <7:4> Set VBI data type for even field (Line 275 for 525 system. Line 325 for 625 system) VBI Data Type Configuration register Line 13 (R/W) [VBILINE13] vbil13o <3:0> Set VBI data type for odd field vbil13e <7:4> Set VBI data type for even field (Line 276 for 525 system. Line 326 for 625 system) VBI Data Type Configuration register Line 14 (R/W) [VBILINE14] vbil14o <3:0> Set VBI data type for odd field vbil14e <7:4> Set VBI data type for even field (Line 277 for 525 system. Line 327 for 625 system) VBI Data Type Configuration register Line 15 (R/W) [VBILINE15] vbil15o <3:0> Set VBI data type for odd field March 8, 2005 35
44
45
46
47
48
49
4A
4B
(c)2004 by AverLogic Technologies, Corp.Version 1.0
AL240
vbil15e 4C
<7:4> Set VBI data type for even field (Line 278 for 525 system. Line 328 for 625 system)
VBI Data Type Configuration register Line 16 (R/W) [VBILINE16] vbil16o <3:0> Set VBI data type for odd field vbil16e <7:4> Set VBI data type for even field (Line 279 for 525 system. Line 329 for 625 system) VBI Data Type Configuration register Line 17 (R/W) [VBILINE17] vbil17o <3:0> Set VBI data type for odd field vbil17e <7:4> Set VBI data type for even field (Line 280 for 525 system. Line 330 for 625 system) VBI Data Type Configuration register Line 18 (R/W) [VBILINE18] vbil18o <3:0> Set VBI data type for odd field vbil18e <7:4> Set VBI data type for even field (Line 281 for 525 system. Line 331 for 625 system) VBI Data Type Configuration register Line 19 (R/W) [VBILINE19] vbil19o <3:0> Set VBI data type for odd field vbil19e <7:4> Set VBI data type for even field (Line 282 for 525 system. Line 332 for 625 system) VBI Data Type Configuration register Line 20 (R/W) [VBILINE20] vbil20o <3:0> Set VBI data type for odd field vbil20e <7:4> Set VBI data type for even field (Line 283 for 525 system. Line 333 for 625 system) VBI Data Type Configuration register Line 21 (R/W) [VBILINE21] vbil21o <3:0> Set VBI data type for odd field vbil21e <7:4> Set VBI data type for even field (Line 284 for 525 system. Line 334 for 625 system) VBI Data Type Configuration register Line 22 (R/W) [VBILINE22] vbil22o <3:0> Set VBI data type for odd field vbil22e <7:4> Set VBI data type for even field (Line 285 for 525 system. Line 335 for 625 system) VBI Data Type Configuration register Line 23 (R/W) [VBILINE23] vbil23o <3:0> Set VBI data type for odd field vbil23e <7:4> Set VBI data type for even field (Line 286 for 525 system. Line 336 for 625 system) VBI Data Type Configuration register for remaining lines (R/W) [VBILINE24] vbil24o <3:0> Set VBI data type for odd field March 8, 2005 36
4D
4E
4F
50
51
52
53
54
(c)2004 by AverLogic Technologies, Corp.Version 1.0
AL240
vbil24e 55
<7:4> Set VBI data type for even field (line 287 for 525 system, line 338 for 625 system)
VBI Data Type Configuration register for remaining lines (R/W) [VBILINE25] vbil25o <3:0> Set VBI data type for odd field vbil25e <7:4> Set VBI data type for even field (line 288 for 525 system, line 338 for 625 system) VBI Data Type Configuration register for remaining lines (R/W) [VBILINE26] vbil26o <3:0> Set VBI data type for the lines in the odd field except line 7 to line 25 vbil26e <7:4> Set VBI data type for all the lines in the even field except lines 270 to 288 for 525 system, or lines 329 to 338 for 625 system VBI Loop Filter I Gain Register 0 (R/W) [VBIIGAIN0] vbi_cc_lpfil _gain <23:0> Loop filter gain for close-caption Recommend Setting: Close Caption = 6 Gemstar Close Caption = 5 Reserved <3> Reserved vbi_tele_lpfil_gain <6:4> Loop filter gain for teletext VBI Loop Filter I Gain Register 1 (R/W) [VBIIGAIN1] vbi_wss625_lpfil_ <2:0> Loop filter gain for wss625 gain Reserved <7:3> Reserved Upper Byte VBI Close Caption DTO Register (R/W) [CCDTOINC] vbi_caption_dto <7:0> Bit <15:8> of the 16-bit DTO incremental value for close-caption clock recovery circuit. Lower Byte VBI Close Caption DTO Register (R/W) [CCDTOINC] vbi_caption_dto <7:0> Bit <7:0> of the 16-bit DTO incremental value for close-caption clock recovery circuit Upper Byte VBI Teletext DTO Register (R/W) [TELDTOINC] vbi_teletext_dto <7:0> Bits<15:8> of the 16-bit DTO incremental value for teletext clock recovery circuit. (default = 12DBh) Lower Byte VBI Teletext DTO Register (R/W) [TELDTOINC] vbi_teletext_dto <7:0> Bits<7:0> of 16-bit DTO incremental value for teletext clock recovery circuit March 8, 2005 37
56
57
58
59
5A
5B
5C
(c)2004 by AverLogic Technologies, Corp.Version 1.0
AL240
5D
Upper Byte VBI WSS625/WSSJ DTO Register (R/W) [WSSDTOINC] vbi_wss625_dto <7:0> Bits<15:8> of 16-bit DTO incremental value for wss625 or wssj clock recovery circuit. Lower Byte VBI WSS625/WSSJ DTO Register (R/W) [WSSDTOINC] vbi_wss625_dto <7:0> Bits<7:0> of 16-bit DTO incremental value for wss625/wssj clock recovery circuit. VBI Close Caption Data 1 Register (R/W) [CCFSTART] caption_frame_start <7:0> The frame start for the close caption VBI Close Caption Data 1 Register (R/W) [WSSFSTART] wss625_frame_start<7:0> The frame start for the wss625 or wssj Recommend Setting: wss625 = B4h (default) Wssj = 64h VBI Close Caption Data 1 Register (R/W) [TELFSTART] teletext_frame_start <7:0> The frame start for the TELETEXT Standard
TELE625A TELE625B TELE625C TELE625D TELE525B TELE525C TELE525D
5E
5F 60
61
Programming Value
34h 34h 34h 34h 35h 35h 35h
62 63 64
VBI Close Caption Data 1 Register (R) [CCDATA1] ccdata1 <7:0> Close caption data byte 1 VBI Close Caption Data 2 Register (R) [CCDATA2] ccdata2 <7:0> Close caption data byte 2 VBI Close Caption Data 1 Register (R/W) [VBINOISETH] vbi_noise_th <7:0> The noise level for the VBI line thus anything below the threshold is zero for data slicing. It specified the lowest level of the adaptive slicer level when there is no VBI data. VBI Data Status Register (R) [VBISTATUS] cc_rdy <0> Close caption data register data. This bit is set to 1 if both CCDATA registers contain the valid close March 8, 2005 38
65
(c)2004 by AverLogic Technologies, Corp.Version 1.0
AL240
wss_rdy
Reserved 66 67
caption data. This bit will be reset to 0 during system reset. It will also be cleared at the beginning of a new field. <1> WSS data register data valid. This bit is set to 1 if all the WSS registers contain the valid WSS data. This bit will be reset to 0 during system reset. It will also be cleared at the beginning of a new field. <7:2> Reserved
VBI Caption Start Register (R/W) [CCSTART] caption_start <7:0> Close caption start. The unit is hcount value. VBI WSS625/WSSJ Start Register (R/W) [WSSSTART] wss625_start <7:0> Wide screen signaling 625 or WSSJ/CGMS start. The Unit is hcount value. Recommend Setting: WSS625 = 64h (default) WSSJ = 5Ah VBI Teletext Start Register (R/W) [TELSTART] teletext_start <7:0> Teletext start. The unit is hcount value. (default = 5Ah) Standard
TELE625A TELE625B TELE625C TELE625D TELE525B TELE525C TELE525D
68
Programming Value
32h 32h 32h 32h 28h 28h 28h
69 6A 6B 6C
Horizontal Sync Start (R/W) [HSSTART] hs_start <7:0> Bits<7:0> of output Hsync starting point Horizontal Sync Width (R/W) [HSWIDTH] hs_width <7:0> Bits<7:0> of output Hsync width Vertical Sync Start (R/W) [VSSTART] vs_start <7:0> Bits<7:0> of output Vsync starting line Vertical Sync Width (R/W) [VSWIDTH] vs_width <7:0> Bits<7:0> of output Vsync width VBI WSS Data 2 Register (R) [WSSDATA2] March 8, 2005 39
6D
(c)2004 by AverLogic Technologies, Corp.Version 1.0
AL240
wssdata2 6E 6F
<7:0> Wide screen signaling data (WSSJ) byte 2
VBI WSS Data 1 Register (R) [WSSDATA1] wssdata1 <7:0> Wide screen signaling data (WSS625/WSSJ) byte 1 VBI WSS Data 0 Register (R) [WSSDATA0] wssdata0 <7:0> Wide screen signaling data (WSS625/WSSJ) byte 0 Horizontal Sync DTO Increment Status (R) [HSDTOINCSTATUS] status_hdto_inc <5:0> Bits<29:24> of 30-bit-wide horizontal sync DTO increment. Reserved <7:6> Reserved Horizontal Sync DTO Increment Status (R) [HSDTOINCSTATUS] status_hdto_inc <7:0> Bits<23:16> of 30-bit-wide horizontal sync DTO increment. Horizontal sync DTO Increment Status (R) [HSDTOINCSTATUS] status_hdto_inc <7:0> Bits<15:8> of 30-bit-wide horizontal sync DTO increment. Horizontal Sync DTO Increment Status (R) [HSDTOINCSTATUS] status_hdto_inc <7:0> Bits<7:0> of 30-bit-wide horizontal sync DTO increment. Chroma Sync DTO Increment Status (R) [CSDTOINCSTATUS] status_cdto_inc <5:0> Bits<29:24> of the 30-bit-wide chroma sync DTO increment. Reserved <7:6> Reserved Chroma Sync DTO Increment Status (R) [CSDTOINCSTATUS] status_cdto_Inc <7:0> Bits<23:16> of the 30-bit-wide chroma sync DTO increment. Chroma Sync DTO Increment Status (R) [CSDTOINCSTATUS] status_cdto_inc <7:0> Bits<15:8> of the 30-bit-wide chroma sync DTO increment. Chroma Sync DTO Increment Status (R) [CSDTOINCSTATUS] status_cdto_inc <7:0> Bits<7:0> of the 30-bit-wide chroma sync DTO increment. AGC Gain Status MSB (R) [AGCSTATUS] status_agc_again <7:0> These bits contain the MSB of the AGC gain value. March 8, 2005 40
70
71
72
73
74
75
76
77
78
(c)2004 by AverLogic Technologies, Corp.Version 1.0
AL240
79 7A 7B
AGC Gain Status LSB (R) [AGCSTATUS] status_agc_dgain <7:0> These bits contain the LSB of the AGC gain value. Chroma Magnitude Status (R) [CMAGSTATUS] status_cmag <7:0> This bits contain the chroma magnitude Chroma Gain Status MSB (R) [CGAINSTATUS] status_cgain <5:0> Bits<13:8> of the chroma gain Reserved <7:6> Reserved Chroma Gain Status LSB (R) [CGAINSTATUS] status_cgain <7:0> Bits<7:0> of the chroma gain Cordic Frequency Status (R) [CORDICFSTATUS] status_cordic_freq <7:0> SECAM cordic frequency Noise Status (R) [NOISESTATUS] status_noise <7:0> Indicates how noisy the signal is. Larger values indicate noisier signals. It is used in conjunction with programmable register 05h, "noise_thresh" and status bit 3C<3>h, "noisy".
7C 7D 7F
Luma Peaking Register 80 Comb Filter Threshold 1 (R/W) [COMBFLTTH] peak_en <0> The luma horizontal peaking control around the color subcarrier frequency 0 Disabled (default) 1 Enabled peak_gain <3:1> The gain for the horizontal peaking control. It allows adjustable gain to the luma around the color subcarrier frequency (default = 2). peak_range <5:4> The range of peak_gain. 00 1 (default) 01 2 10 4 11 8 Ypeak = Y + YH * (peak_gain/peak_range) where Y is the luma and YH is the high frequency luma only Reserved <7:6> Reserved
(c)2004 by AverLogic Technologies, Corp.Version 1.0
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AL240
Adaptive Comb Filter Configuration Register 82 Comb Filter Configuration (R/W) [COMBFLTCONFIG] palsw_level <1:0> Used to determine how many incorrect lines are used for the PAL switch circuit before switching. Use a higher level for noisy signals. (default = 2h) Reserved <3:2> Reserved comb_wide_band <4> Used to select the bandpass filter used in the combfilter. It should be set to 1 for PAL mode. (default = 0h) pal_perr_auto_en <5> Turn on the pal_perr when VCR signals are detected. 0 Off (default) 1 On pal_perr <6> Used to reduce phase-error artifacts in the comb filter's luma-path. It should be set for VCR signals (default = 1). Reserved <7> Reserved Chip Version (R) [VERSION] Version <3:0> Chip version Fixed number <7:4> 4 Output Format Control (R/W) [OFORMAT] Oformat <3:0> Output format & Test mode select YC_OE <4> DO[7:0] bus output enable control 0 Enable 1 Disable Reserve <6:5> Reserved llc_inv <7> Invert llc output (default = 0) 0 LLC 1 LLC delayed by 180 degree RTSO[0] output enable (R/W) [RTSO[0]&TSTPAT] RTSO[0]_CTL <4:0> Control RTSO[0] output. It works when oformat<2> = 0 Reserved <7:5> Default `000' for normal operation RTSO[1] output control (R/W) [RTSO[1]] RTSO[1]_CTL <4:0> Control RTSO[1] output. It works when oformat[2] =0 Reserved <7:5> Reserved RTSO[2] output control (R/W) [RTSO[2]] March 8, 2005 42
B0
B1
B2
B3
B4
(c)2004 by AverLogic Technologies, Corp.Version 1.0
AL240
RTSO[2]_CTL Reserved B5
<4:0> Control RTSO[2] output. It works when oformat[2] =0 <7:5> Reserved
RTSO[3] output control (R/W) [RTSO[3]] RTSO[3]_CTL <4:0> Control RTSO[3] output. It works when oformat[2] =0 Reserved <7:5> Reserved RTSO[4] output control (R/W) [RTSO[4]] RTSO[4]_CTL <4:0> Control RTSO[4] output. It works when oformat[2] =0 Reserved <7:5> Reserved AFE Input & Fast switch control (R/W) [AFEIN&FSW] afe_in_sel <1:0> Afe_in_sel , and yc_reg select analog input pins when hardware switching pin is disabled (B7h bit 3 fast_sw = 0). The selections are; yc_src afe_in_sel Input pin name 0 00 AI0 0 01 AI1 0 10 AI2 0 11 AI3 1 00 AI0/AI2 (Y/C) 1 01 AI1/AI3 (Y/C) Note: for S-video input, set adaptive_mode (03h) to "011" Reserved <2> Fast_sw <3> When this bit is set to `1', AL240 turns into "Hardware switch" mode. In this mode, AL240 assumes input sources are CVBS signals (CVBS1~4) and selected by FSW[1:0] pins 0 Software switching for input 1 FSW[1] and FSW[0] input switching control Reserved <7:4> Reserved
B6
B7
PLL Registers B8 PLL control 0 (R/W) [PLLCTRL0] PLL_OE <0> Output enable 0 Normal operation 1 No output PLL_Pd <1> Power down PLL 0 Normal operation 1 Power down PLL_Bp <2> Bypass PLL, i.e. fout = fin (c)2004 by AverLogic Technologies, Corp.Version 1.0 March 8, 2005 43
AL240
LLC_Divide Reserved BA PLL_NF PLL_OD Reserved BB BC BD BE BF fifo_level_gain AFE Registers C0
0 Normal operation 1 Bypass <6:3> LLC circuit divider Value <7:4> Reserved PLL control 2 (R/W) [PLLCTRL 2] <5:0> Feedback divider setting <6> Output divided by 2 0 No divided 1 Divided by 2 <7> Reserved
LLC DTO increment (R/W) [LLCDTOINC 3] llc_dto_inc[31:24] <7:0> LLC DTO increment bit <31: 24> LLC DTO increment (R/W) [LLCDTOINC 2] llc_dto_inc[23:16] <7:0> LLC DTO increment bit <23: 16> LLC DTO increment (R/W) [LLCDTOINC 1] llc_dto_inc[15:8] <7:0> LLC DTO increment bit <15: 8> LLC DTO increment (R/W) [LLCDTOINC 0] llc_dto_inc[7:0] <7:0> LLC DTO increment bit <7: 0> FIFO Gain Level (R/W) [FIFOGAIN] <3:0> Output data FIFO level gain adjustment <3: 0>
DC restore circuit control 0 (R/W) [DCRSTOCTRL 0] dcrestore_gain <1:0> DC-restore gain 00: 1x gain (default) 01: 1/2x gain 10: 1/4x gain 11: 1/8x gain syncmid_filter_en <2> Filtering of the sync mid-point 0: no filter 1: filter (default) syncmid_nobp_en <3> Sampling of sync mid-points when back-porches are not detected 0: no sample (default) 1: sample dcrestore_bp_delay <5:4> Relative sync-tip to back-porch delay adjustment. The unit bits are adjusted in March 8, 2005 44
(c)2004 by AverLogic Technologies, Corp.Version 1.0
AL240
"dcrestore_accum_width" (register 0Ch). 01: (default) dcrestore_kill_en <6> Sampling of bad back-porch values 0: don't kill; sample bad back-porches 1: kill; don't sample bad back-porches (default) dcrestore_no_bad_bp Use accumulated bad back-porch values 0: use accumulated bad back-porch values 1: don't use accumulated bad back-porch values (default) C1 DC restore circuit control 1 (R/W) [DCRSTOCTRL 1] dcrestore_accum_w <5:0> Number of samples to be accumulated when idth calculating the sync-tip and back-porch levels (default= 1Bh). dcrestore_scale_rati <7:6> Scaling of the input signal to the DC-restore and o sync-slicing sub-modules. 00: 1x (default) 01: 2x 02: 4x 03: reserved Manual gain control (R/W) [MANUALGAIN] hmgc <7:0> Manual gain adjustment (hagc_en= 0, register 02h). A value of 64 represents a unit gain, 32 represent a one-half gain, and 128 denote a double gain. (default = 40h) DC restore hmid (R/W) [DCRSTOHMID] dcrestore_hmid <7:0> Set the horizontal mid-point used to reset the DCrestore accumulators. The 2's complement values is relative to the actual horizontal mid-point (default=7h) FIFO level (R) [FIFOLEVEL] fifo_leve <7:0> Output data FIFO level status Data path swap (R/W) [DATASWAP] Reserved <1:0> cbcr_updn_swap <2> Swap CbCr up/dn signals crupdn_swap <3> Swap crup/crdn signals cbupdn_swap <4> Swap cbup/cbdn signals yupdn_swap <5> Swap Yup/Ydn signals yc_digital_swap <6> Swap yadcdata[9:0] and cadcdata[9:0]. External MUX, outside AFE March 8, 2005 45
C2
C4
D0 D4
(c)2004 by AverLogic Technologies, Corp.Version 1.0
AL240
D5
Y/C Gain control (R/W) [YCGAIN] cgain <1:0> Adjusts PGA amplifier for C input gain level 00: 0.5x ; input level > 1.5V (Vp-p) 01: 1x; input level between 0.75V ~ 1.5V (Vp-p) 10: 2x; input level between 0.375V ~ 1.5V (Vp-p) 11: 4x; input level < 0.375V ygain <3:2> Adjusts PGA amplifier for Y input gain level 00: 0.5x; input level > 1.5V (Vp-p) 01: 1x; input level between 0.75V ~ 1.5V (Vp-p) 10: 2x; input level between 0.375V ~ 1.5V (Vp-p) 11: 4x; input level < 0.375V Write enable (R/W) [WRITEENABLE] write_enable <7:0> For registers write operation, set register Feh = FFh (default = 0) Reference setting values
NTSC-M FF 00 01 4E 00 DD 20 8A 2C 2D D1 74 5D 2B 33 33 33 82 22 61 48 50 42 6F 90 00 18 35 NTSC-443 FF 00 01 4E 03 DD 20 8A 2C 38 C0 14 F8 2B 33 33 33 82 22 61 48 50 42 6F 90 00 18 35 PAL-I FF 32 00 4E 00 DC 20 67 2C 38 C0 14 F8 2B 33 33 33 84 2A C1 48 50 52 6F 90 00 18 35 PAL-M FF 04 00 4E 00 DD 20 67 2C 2D C4 90 50 2B 33 33 33 82 22 61 48 50 42 6F 90 00 18 35 PAL-CN FF 36 00 4E 00 DC 20 67 2C 2D D9 AE 92 2B 33 33 33 84 2A C1 48 50 42 6F 90 00 18 35 PAL-60 FF 02 00 4E 00 DC 20 67 2C 38 C0 14 F8 2B 33 33 33 82 22 61 48 50 42 6F 90 00 18 35 SECAM FF 38 00 4E 00 DC 20 67 25 36 DC 5D 63 2B 33 33 33 84 2A C1 48 50 42 EF 90 00 18 35
FE
9.3
Register RFE (Hex) R00 (Hex) R01 (Hex) R02 (Hex) R03 (Hex) R04 (Hex) R07 (Hex) R0C (Hex) R0F (Hex) R18 (Hex) R19 (Hex) R1A (Hex) R1B (Hex) R1C (Hex) R1D (Hex) R1E (Hex) R1F (Hex) R2E (Hex) R30 (Hex) R31 (Hex) R69 (Hex) R6A (Hex) R82 (Hex) R83 (Hex) RB1 (Hex) RB7 (Hex) RBA (Hex) RBB (Hex)
(c)2004 by AverLogic Technologies, Corp.Version 1.0
March 8, 2005
46
AL240 RBC (Hex) RBF (Hex) RD4 (Hex) RD5 (Hex) R3F (Hex) 2B 03 3C 00 00 2B 03 3C 00 00 2B 03 3C 00 00 2B 03 3C 00 00 2B 03 3C 00 00 2B 03 3C 00 00 2B 03 3C 00 00
10 Output Timing
10.1 Timing Diagram
LLC DO[7:0] Cb HREF Y Cr
Y
FF
00
00
EAV
00
FF
00
00
SAV
Cb
Y
Cr
Y
Figure 7: ITU-R.BT656 8-bit Output Timing
tCK LLC tCKH tCKL tf tPD tr
DO tOH
Figure 8: Data Output Timing
(c)2004 by AverLogic Technologies, Corp.Version 1.0
March 8, 2005
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AL240
11 Electrical Characteristics
11.1 Absolute Maximum Ratings Under Free-Air Temperature (Excessive ratings are harmful to the lifetime. Only for user guidelines, not tested.)
Parameter AVDD33 DVDD33 AVDD18 DVDD18 VP IO TAMB Tstg Analog front end supply voltage (AVDD to AGND) I/O supply voltage (DVDD to DGND) Analog logic supply voltage (AVDD to AGND) Digital core supply voltage (DVDD to DGND) Input pin voltage (Vp to DGND) Output current Ambient operating temperature Storage temperature 1.8V/3.3V Rating -0.3 ~ +4.5 -0.3 ~ +4.5 -0.3 ~ +2.3 -0.3 ~ +2.3 -0.3 ~ +(VDD+0.3) -20 ~ +20 0 ~ +70 -40 ~ +125 Unit V V V V V mA C C
11.2 Recommended Operating Conditions
Parameter AVDD33 DVDD33 AVDD18 DVDD18 VIH VIL TA Analog front end supply voltage I/O supply voltage Analog logic supply voltage Digital core supply voltage High level input voltage Low level input voltage Operating free-air temperature 1.8V/3.3V Rating Min. +3.0 +3.0 +1.65 +1.65 0.7 VDD 0 0 Typical +3.3 +3.3 +1.8 +1.8 Max. +3.6 +3.6 +2.0 +2.0 VDD 0.3 VDD +70 Unit V V V V V V C
11.3 Crystal Specifications
Rating 20.0000
Parameter Frequency
Unit MHz
(c)2004 by AverLogic Technologies, Corp.Version 1.0
March 8, 2005
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AL240
Frequency Tolerance
50
Ppm
11.4 Analog Front End Processing and A/D Converters
1.8V/3.3V Rating Min. 0.375 6 27 0.5 1 50 66 1 1 Typical Max. 3
Parameter Vi (PP) FB FS DNL INL SNR CS DG DP Input range Band width ADC sample rate DC differential non-linearity DC integral non-linearity Signal-to-noise ratio Channel separation Differential gain Differential Phase
Unit Vpp MHz MHz LSB LSB dB dB % Degrees
11.5 AC Characteristics (VDD = 1.8V/3.3V, Vss=0V, TAMB = 0 to 70C; Some parameters are guaranteed by design only, not production tested)
Parameter 1.8V/3.3V Rating Min. Power Supply Current IDD IDDS P tCK tr tf tPD tOH Operating Current @27MHz Standby Current Power Consumption Output interface timing cycle time for data output (LLC) Rising time for LLC Falling time for LLC Propagation delay for DO in 8-bit output mode Hold time for DO in 8-bit output mode 3 2 18 1.5 1.5 ns ns ns ns ns TBD TBD TBD mA mA mW Typical Max. Unit
(c)2004 by AverLogic Technologies, Corp.Version 1.0
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AL240
12 Application Information:
12.1 Analog Front End connection
GRST SSEL0 SSEL1 DRTSO3 DRTSO4
VCM C1 10uF A C51 0.1uF
AVCC33
VCM 240AI2
VCC33
VCC18
U1
VCMY AI2 AVDDIO AGND CS SSEL0 SSEL1 RTSO3/FSW0 RTSO4/FSW1 DGND DVDDIO
44 43 42 41 40 39 38 37 36 35 34
27MHZ R3 0 No Fit DVDD XIN XOUT DGND DVDD DGND RTSO2 RTSO1 RTSO0 SCL SDA 33 32 31 30 29 28 27 26 25 24 23 XIN XOUT
C7 10uF/16V
C8 0.1uF
240AI3
C3
C4
C5 0.1uF
0.1uF 10uF/16V
VCM 240AI0 240AI1 VCC18 DGND
1 2 3 4 5 6 7 8 9 10 11
AI3 AGND AVDDIO VBG VREFP VREFN VCMC AI0 AI1 DVDD DGND
AVERLOGIC
AL240 QFP-44
DO7 DO6 DO5 DO4 DGND LLC DVDDIO DO3 DO2 DO1 DO0
DRTSO2 DRTSO1 DRTSO0 SCL SDA
C6 0.1uF
A
12 13 14 15 16 17 18 19 20 21 22
AL240
DD7 DD6 DD5 DD4
DD3 DD2 DD1 DD0
LLC
D
DRTSO[4:0] DD[15:0]
DRTSO[4:0] DD[15:0]
VCC18 VCC18 C73 1uF AVCC33 AVCC33 C84 1uF C85 1uF C86 1uF C87 0.1uF C88 0.1uF C89 0.1uF C90 0.1uF C91 0.1uF C74 1uF C75 1uF C76 1uF C77 1uF C78 1uF C79 0.1uF C80 0.1uF
VCC18
C81 0.1uF
C82 0.1uF
C83 100pF L23 D BEAD 0805 A BEAD 0805 VCC33
2,3,6
AVCC33 L22 C92 0.1uF C93 100pF
AGND
Figure 9: Analog Front End
(c)2004 by AverLogic Technologies, Corp.Version 1.0
March 8, 2005
50
AL240
13 Mechanical Drawing 44-PIN QFP
13.1 10x10 mm 44-PIN QFP package
(c)2004 by AverLogic Technologies, Corp.Version 1.0
March 8, 2005
51
AL240
CONTACT INFORMATION
Averlogic Technologies Corp. Taiwan Email: sales@averlogic.com.tw URL: http://www.averlogic.com.tw
Averlogic Technologies, Inc. USA Email: sales_usa@averlogic.com.tw URL: http://www.averlogic.com
(c)2004 by AverLogic Technologies, Corp.Version 1.0
March 8, 2005
52